1. Field of the Invention
The present invention generally relates to filter circuits, and particularly relates to an active filter circuit with a compensated phase delay and a sigma-delta A/D converter utilizing such a circuit.
2. Description of the Related Art
Sigma-delta A/D converters obtain a differential between an analog input signal and a feedback signal fed back after the D/A conversion of the digital output, and performs an A/D conversion with respect to the differential signal after the integration thereof. The circuit portion that performs the A/D conversion of the differential signal after integration may be a low-precision A/D converter having a small number of output bits. For example, a comparator having one bit output may be used for this purpose. In this case, the one-bit digital output of the comparator is D/A-converted and fed back, and a differential between the feedback signal and the analog input signal is obtained and integrated. The integration accumulates differences between the input and the output over time. When the accumulated difference between the input and the output over time exceeds the threshold of the comparator at some point in time, the output of the comparator is inverted.
The feedback signal made by performing D/A conversion on the output “1” of the comparator is 1 V, and the input signal is 0.75 V, for example. The differential, which is equal to −0.25 V, is accumulated through integration. The output of the comparator that receives the integrated signal as its input then changes from “1” to “0” at some point in time. The feed-back signal made by performing D/A conversion on the output “0” of the comparator is 0 V, for example. Since the input signal is 0.75 V, the difference is +0.75 V. The differential (+0.75V) is accumulated by integration. The output of the comparator that receives the integrated signal as its input then changes from “0” to “1” at some point in time. In this manner, the digital output alternates between “0” and “1”.
A rate at which the integrated signal changes by integrating +0.75 V is three times greater than the rate at which the integrated signal changes by integrating −0.25V. As a result, the period during which +0.75 V is being accumulated, i.e., the period during which the digital output is “0”, is one third of the period during which −0.25 V is being accumulated, i.e., the period during which the digital output is “1”. The digital output that alternates between “0” and “1” thus has an average that is equal to 0.75, which precisely represents the input analog potential.
If the digital output is sampled, the sampled digital output in the above example becomes “111011101110 . . . ”, for example. With the over-sampling of the digital output and the averaging by use of a FIR low-pass filter, therefore, the A/D conversion output is obtained with the precision commensurate with the over-sampling rate.
In this manner, the sigma-delta A/D converter provides high precision by its nature, and has an advantage in that most of the processing is performed digitally, with few analog-based parts.
FIG. 1 is a diagram showing the construction of a sigma-delta A/D converter. A sigma-delta A/D converter 10 of FIG. 1 includes an adding/subtracting unit 11, a loop-filter 12, an A/D converter 13, and a DAC (D/A converter) 15. The A/D converter 13 and the DAC 14 operate based on a clock signal CLK. The DAC 14 performs a D/A conversion with respect to the digital output signal for provision as an analog feedback signal to the adding/subtracting unit 11. The adding/subtracting unit 11 obtains a differential between the analog input signal and the feedback signal to supply the differential signal to the A/D converter 13. The loop-filter 12 is a low-pass filter, and has the function to integrate the differential signal supplied from the A/D converter 13. The integrated signal made by integrating the differential signal is supplied from the loop-filter 12 to the A/D converter 13. The A/D converter 13 performs an A/D conversion with respect to the integrated signal for provision as a digital signal output.
The differential signal output from the adding/subtracting unit 11 corresponds to a difference between the input signal and the output signal that is left unrepresented by the limited number of bits of the digital output signal. When an accumulation of this difference grows in the integrated signal, the digital signal output of the A/D converter 13 changes at some point in time. The time period required for the accumulation of the difference and the subsequent change is reciprocal to the difference between the input signal and the output signal that is left unrepresented by the limited number of bits of the digital output signal. Accordingly, a temporal average of the digital output signal of the A/D converter 13 can represent the analog input signal with the precision that exceeds precision achievable by the limited number of bits of the digital output signal. Namely, with the provision of the digital output signal at an over-sampling rate and the averaging of the signal by use of a FIR low-pass filter, it is possible to provide an A/D converter output with the precision commensurate with the over-sampling rate.
In general, a gm-C-type filter is used as the loop-filter 12 in order to achieve desired filter characteristics. The gm-C-type filter typically has the configuration in which a voltage-to-current converting amplifier (OTA: operational transconductance amplifier) is used in the feed-forward path to compensate for phase delay (Lucien J. Breems, “A 1.8-mW CMOS ΣΔ Modulator with Integrates Mixer for A/D Conversion of IF Signals,” IEEE Journal of Solid-State Circuits, Vol. 35, No. 4, 2000).
When a filter having a gain is used in a feedback-loop system as shown in FIG. 1, a phase delay becomes an issue.
FIG. 2 is a diagram for explaining the issue of phase delay. The example shown in FIG. 2 shows a system having two poles. Around each pole, the slope of the gain decreases by 20 dB/dec, and the phase delays by 90 degrees. In a system having two or more poles, the phase ends up delaying 180 degrees on the higher-frequency side. This means that the sign of higher frequency components is reversed between the input and output of the filter with respect to the signals. If the gain is higher than 1 (0 dB) with respect to a frequency having a 180-degree phase delay, the loop undesirably oscillates. A method for compensating for such phase delay includes adding a zero.
FIG. 3 is a diagram for explaining a case in which a zero is added to compensate for phase delay. Around a zero, the gain increases by 20 dB/dec, and the phase advances by 90 degrees. Accordingly, provision of zeros in the filter as many as the number of poles or one less than the number of poles makes it possible to reduce the phase to less than 180 degrees as shown in FIG. 3 while the phase had a 180-degree delay in FIG. 2.
FIGS. 4A and 4B are diagrams showing a construction that compensates for phase by adding zeros in a second-order gm-C-type filter. FIG. 4A illustrates a filter for which no phase compensation is provided. This filter includes voltage-to-current converting amplifiers (OTA) 301 and 302, capacitors 303 and 304, and a resistor 305. The voltage-to-current converting amplifiers 301 and 302 each convert an input voltage signal from voltage to current so as to output a current signal. The respective output currents charge the capacitors 303 and 304 connected to the output nodes. As a result, voltages corresponding to the integration of the respective output currents are obtained. In this manner, a single voltage-to-current converting amplifier and a single capacitor together constitute a single-stage integrator (low-pass filter). The filter configuration shown in FIG. 4A has a problem in that the phase is delayed by 180 degrees on the higher frequency side.
FIG. 4B illustrates a filter for which phase is compensated for by adding zeros. This filter includes voltage-to-current converting amplifiers (OTA) 311 and 312 in addition to the voltage-to-current converting amplifiers (OTA) 301 and 302, the capacitors 303 and 304, and the resistor 305 shown in FIG. 4A. The provision of the feed-forward voltage-to-current converting amplifiers 311 and 312 makes it possible to add zeros to compensate for phase delay.
FIG. 5 is a diagram showing the construction of a fourth-order filter for which phase is compensated for. The filter shown in FIG. 5 includes voltage-to-current converting amplifiers (OTA) 401 through 404, capacitors 405 through 408, voltage-to-current converting amplifiers (OTA) 409 through 412, and a resistor 413. The provision of the feed-forward voltage-to-current converting amplifiers 409 through 412 makes it possible to add zeros to compensate for phase delay. This filter has four poles and three zeros, and is designed to have a 90-degree phase delay on the higher frequency side.
The second-order filter configuration shown in FIG. 4B uses two feed-forward voltage-to-current converting amplifiers for the purpose of phase compensation, and the fourth-order filter configuration shown in FIG. 5 uses four feed-forward voltage-to-current converting amplifiers for the purpose of phase compensation. In this manner, an n-th order filter configuration generally has n feed-forward voltage-to-current converting amplifiers added thereto. These feed-forward voltage-to-current converting amplifiers for the purpose of phase compensation consume electric power in the same manner as the voltage-to-current converting amplifiers for the purpose of integration provided at the respective stages. Accordingly, power consumption by the amplifiers doubles in the filter having the phase-compensated configuration.
Accordingly, there is a need for a gm-C-type filter that achieves phase compensation while suppressing power consumption.